SRAM Design - PDK Support Engineer
Job Details:
Job Description:
At Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products to the marketplace.
You will directly drive and work with DE cross-teams to ensure design-kit leadership for customer enablement in cutting edge technologies.
You will work with customers to outline critical requirements, collaborate with Intel internal partners to define scope, plan, execution, and innovate competitive solutions to meets customer needs.
This role is to support Intel SRAM PPA (Performance, Power, Area) analysis in advanced process nodes, from bit-cell to macro.
You will collaborate with SRAM designers to outline industry standard indicators for SRAM products.
You will perform verification simulations and work with SRAM compilers.
You will analyze differences for each PPA indicator with each PDK migration as well as interpret root cause for any arising issues.
You will oversee different SRAM bit-cell offerings and perform competitive benchmarking.
You will be 1st line customer support for any SRAM issue to debug, identify root cause, and work with designers to develop solutions.
Also, you will need to work with teams to perform regression analysis on SRAM macros and regularly evaluate SRAM design/collateral integrity and quality.
As a DEAS (Design Enablement Application and Support) key member, you will need to have good communication skills to interact with customers directly, apply analytical problem-solving techniques to identify key requests, and work in a team environment with DE stakeholders to support and enable customer success.
Qualifications:
Minimum qualifications are required to be initially considered for this position.
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Minimum
Qualifications:
Candidate will possess a BS degree with 4
years of experience, or MS degree 3
years of experience, or PhD degree with 1
years of experience in Electrical/Computer Engineering, or related STEM fields.
2
years of experience in the following:
- SRAM designs, in terms of circuit design, layout, physical verification, and timing simulation.
- SRAM's memory design techniques, and macro/block development.
Preferred
Qualifications:
- Experienced in simulation of SRAM bit-cells to extract key indicators such as Iread, Iwrite, Vccmin, SNM, etc.
- Knowledge of SRAM bit-cel operations, all functional parts of the SRAM macro, and familiar with what industry indicators are used to evaluate SRAM bit-cell or MACRO PPA.
- Ability to analyze issues, solve problems, and to bring the design to closure.
Job Type:
Experienced HireShift:
Shift 1 (United States of America)Primary Location:
US, California, Santa ClaraAdditional Locations:
US, Arizona, Phoenix, US, California, San Jose, US, Oregon, Hillsboro, US, Texas, AustinBusiness group:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.
Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore s Law to bring smart, connected devices to every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of TrustN/A
Benefits:
We offer a total compensation package that ranks among the best in the industry.
It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.
Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in US, California:
$123,419.
00-$185,123.
00Salary range dependent on a number of factors including location and experience.
Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
In certain circumstances the work model may change to accommodate business needs.
SummaryLocation:
US, California, Santa Clara; US, Oregon, Hillsboro; US, Texas, Austin; US, Arizona, Phoenix; US, California, San JoseType:
Full time.
Estimated Salary: $20 to $28 per hour based on qualifications.
Job Description:
At Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products to the marketplace.
You will directly drive and work with DE cross-teams to ensure design-kit leadership for customer enablement in cutting edge technologies.
You will work with customers to outline critical requirements, collaborate with Intel internal partners to define scope, plan, execution, and innovate competitive solutions to meets customer needs.
This role is to support Intel SRAM PPA (Performance, Power, Area) analysis in advanced process nodes, from bit-cell to macro.
You will collaborate with SRAM designers to outline industry standard indicators for SRAM products.
You will perform verification simulations and work with SRAM compilers.
You will analyze differences for each PPA indicator with each PDK migration as well as interpret root cause for any arising issues.
You will oversee different SRAM bit-cell offerings and perform competitive benchmarking.
You will be 1st line customer support for any SRAM issue to debug, identify root cause, and work with designers to develop solutions.
Also, you will need to work with teams to perform regression analysis on SRAM macros and regularly evaluate SRAM design/collateral integrity and quality.
As a DEAS (Design Enablement Application and Support) key member, you will need to have good communication skills to interact with customers directly, apply analytical problem-solving techniques to identify key requests, and work in a team environment with DE stakeholders to support and enable customer success.
Qualifications:
Minimum qualifications are required to be initially considered for this position.
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Minimum
Qualifications:
Candidate will possess a BS degree with 4
years of experience, or MS degree 3
years of experience, or PhD degree with 1
years of experience in Electrical/Computer Engineering, or related STEM fields.
2
years of experience in the following:
- SRAM designs, in terms of circuit design, layout, physical verification, and timing simulation.
- SRAM's memory design techniques, and macro/block development.
Preferred
Qualifications:
- Experienced in simulation of SRAM bit-cells to extract key indicators such as Iread, Iwrite, Vccmin, SNM, etc.
- Knowledge of SRAM bit-cel operations, all functional parts of the SRAM macro, and familiar with what industry indicators are used to evaluate SRAM bit-cell or MACRO PPA.
- Ability to analyze issues, solve problems, and to bring the design to closure.
Job Type:
Experienced HireShift:
Shift 1 (United States of America)Primary Location:
US, California, Santa ClaraAdditional Locations:
US, Arizona, Phoenix, US, California, San Jose, US, Oregon, Hillsboro, US, Texas, AustinBusiness group:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.
Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore s Law to bring smart, connected devices to every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of TrustN/A
Benefits:
We offer a total compensation package that ranks among the best in the industry.
It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.
Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in US, California:
$123,419.
00-$185,123.
00Salary range dependent on a number of factors including location and experience.
Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
In certain circumstances the work model may change to accommodate business needs.
SummaryLocation:
US, California, Santa Clara; US, Oregon, Hillsboro; US, Texas, Austin; US, Arizona, Phoenix; US, California, San JoseType:
Full time.
Estimated Salary: $20 to $28 per hour based on qualifications.
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