Engineer: FPGA/RTL Design - III: 24-00725
Primary Skills:
RTL Design, VLSI, System Verilog, Logic Design, Validation, and TestingContract Type:
W2 OnlyDuration:
6
Months (Possible Extension)Location:
Hillsboro, OR (100% Remote)Pay Range:
$60 -$65 Per HourWork for the largest semiconductor manufacturing company. JOB
Responsibilities:
You will be involved in deep sub-micron IC logic and VLSI design, validation, development, developing, verifying, and validating competitive solutions with Client's PROM circuit technology for use in mobile, IOT, client, network, and server segments Job responsibilities include RTL design and validation for Fuse Soft IP, developing tests for designs and validating PROM Sub-system, IP, and Controller designs, identifying potential design limitations and bugs that can impact design margin and component yield Provides Post-Si support, including but not limited to characterization, test definition, debugging product returns as well as reviewing and dispositioning results. JOB REQUIREMENTS:
Bachelor's degree in electrical engineering with 3
experience or master's degree in electrical engineering or related field with 2
year experience. Experience in Logic design, validation, and testing, including but not limited to:
Micro-architecture definition of design features, test plan creation and functional verification. Effective behavioral modeling and testing of circuits in Verilog and System Verilog, as well as logical equivalence verification between Schematic and Verilog models. UPF (Unified Power Format) creation using low power techniques and handling multiple power domain design. Knowledge of Clock Domain Crossing, Design for Test, Register Description Language. Experience in test bench creation to generate test patterns and vectors. Experience with FEV (Formal Equivalence Verification) and GLS (Gate Level Simulations) ABOUT AKRAYAAkraya is an award-winning IT staffing firm and the staffing partner of choice for many leading companies across the USAkraya was recently voted as a 2021 Best Staffing Firm to Temp for by Staffing Industry Analysts and voted by our employees and consultants as a 2022 Glassdoor Best Places to Work Engineer:
FPGA/RTL Design - III:
24-00725 Recommended Skills Debugging Earthworks Roads, Pavements And Highways Electrical Engineering Functional Testing Microarchitecture Subsystems Apply to this job. Think you're the perfect candidate? Apply on company site $(document).ready( function() $(#ads-desktop-placeholder).html(
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n Estimated Salary: $20 to $28 per hour based on qualifications.
RTL Design, VLSI, System Verilog, Logic Design, Validation, and TestingContract Type:
W2 OnlyDuration:
6
Months (Possible Extension)Location:
Hillsboro, OR (100% Remote)Pay Range:
$60 -$65 Per HourWork for the largest semiconductor manufacturing company. JOB
Responsibilities:
You will be involved in deep sub-micron IC logic and VLSI design, validation, development, developing, verifying, and validating competitive solutions with Client's PROM circuit technology for use in mobile, IOT, client, network, and server segments Job responsibilities include RTL design and validation for Fuse Soft IP, developing tests for designs and validating PROM Sub-system, IP, and Controller designs, identifying potential design limitations and bugs that can impact design margin and component yield Provides Post-Si support, including but not limited to characterization, test definition, debugging product returns as well as reviewing and dispositioning results. JOB REQUIREMENTS:
Bachelor's degree in electrical engineering with 3
experience or master's degree in electrical engineering or related field with 2
year experience. Experience in Logic design, validation, and testing, including but not limited to:
Micro-architecture definition of design features, test plan creation and functional verification. Effective behavioral modeling and testing of circuits in Verilog and System Verilog, as well as logical equivalence verification between Schematic and Verilog models. UPF (Unified Power Format) creation using low power techniques and handling multiple power domain design. Knowledge of Clock Domain Crossing, Design for Test, Register Description Language. Experience in test bench creation to generate test patterns and vectors. Experience with FEV (Formal Equivalence Verification) and GLS (Gate Level Simulations) ABOUT AKRAYAAkraya is an award-winning IT staffing firm and the staffing partner of choice for many leading companies across the USAkraya was recently voted as a 2021 Best Staffing Firm to Temp for by Staffing Industry Analysts and voted by our employees and consultants as a 2022 Glassdoor Best Places to Work Engineer:
FPGA/RTL Design - III:
24-00725 Recommended Skills Debugging Earthworks Roads, Pavements And Highways Electrical Engineering Functional Testing Microarchitecture Subsystems Apply to this job. Think you're the perfect candidate? Apply on company site $(document).ready( function() $(#ads-desktop-placeholder).html(
n
n
n Estimated Salary: $20 to $28 per hour based on qualifications.
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